1. Field of the Invention
The present invention relates to memory management systems for computers and more specifically, to memory segmentation systems for microprocessors with increased cache memory coherency.
2. Art Background
Memory management is a hardware mechanism which lets operating systems create simplified environments for running programs such that when several programs are running at the same time, they may each be given an independent address space to avoid interference with each other. Memory management typically consists of segmentation and paging. Segmentation is used to give each program several independent, protected address spaces ("segments"). Paging is used to support an environment where large address spaces are simulated using a small amount of random access memory ("RAM") and some disk storage. System designers may choose to use either or both of these mechanisms. When several programs are running at the same time, either mechanism can be used to protect programs against interference from other programs.
Segmentation allows memory to be completely unstructured and simple, like the memory model of a simple 8-bit processor, or highly structured with address translation and protection. Each segment is an independent, protected address space. Access to segments is controlled by data which describes its size, the privilege level required to access it, the kinds of memory references which can be made to it (instruction fetch, stack push or pop, read operation, write operation, etc.), and whether it is present in memory.
Reference is now made to FIG. 1A, where a pictorial representation of memory address translation mechanism is shown. Segmentation mechanism 105 translates segmented (logical) address 100 into an address for a continuous, unsegmented address space, called linear address 110. If paging is enabled, paging mechanism 115 translates linear address 110 into physical address 120. If paging 115 is not enabled, linear address 110 is used as physical address 120. Physical address 120 ultimately appears on the address bus coming out of the processor.
An example of a memory management system can be found implemented in the i486.TM. microprocessors manufactured by Intel Corporation of Santa Clara, Calif., the Assignee of the present application. In the i486.TM. microprocessors, a logical address consists of the 16-bit segment selector for its segment and a 32-bit offset into the segment. With reference to FIG. 1A, logical address 100 is translated into linear address 110 by adding offset 101 to base address 103 of the segment. Base address 103 is derived from segment descriptor 104, which is a data structure in memory which provides the size and location of a segment, as well as access control information. For example, the segment descriptor in a i486.TM. microprocessor comes from one of two tables, the global descriptor table (GDT) or the local descriptor table (LDT). There is one GDT for all programs in the system, and one LDT for each separate program or task being run. If the operating system allows, different programs can share the same LDT. The system also may be set up with no LDTs; all programs will then use the GDT. For more information with regard to the i486.TM. microprocessors, please refer to i486.TM. Microprocessor: Programmer's Reference Manual, available from Intel Corporation, Santa Clara, Calif.
The translated address is linear address 110. If paging mechanism is not used, linear address 110 is physical address 120. If paging is used, a second level of address translation is needed to produce physical address 120.
Reference is still made to FIG. 1A. Segment selector 102 is shown pointing to segment descriptor 104 which defines a segment. A program in the i486.TM. microprocessors may call for more segments than those segment selectors currently occupying segment registers. When this is true, the program uses forms of MOVE instructions to change the contents of the segment registers when it needs to access a new segment. As shown in FIG. 1B, segment selector 132 identifies a segment descriptor by specifying descriptor tables 133 and descriptor index 134 within that table.
Reference is now made to FIG. 2, where a descriptor format in the i486.TM. microprocessor is illustrated. However, because the descriptor format needs to provide backward compatibility for prior processor architectures, the descriptor format becomes scrambled when it is stored in memory. To simplify internal processor operations, a raw scrambled descriptor needs to be transformed into a unscrambled descriptor. The transformation of a scrambled segment descriptor 300 into an unscrambled segment descriptor 310 for the i486.TM. processors is illustrated in FIG. 3.
Further, a segment descriptor cache as described in the above identified co-pending application can be used to retain previously fetched, unscrambled, and protection tested descriptors such that on subsequent segment register loads, the descriptor can be sourced from the segment descriptor cache and loaded directly into the segment descriptor register file in one clock cycle, thus bypassing all of the work and overhead usually associated with segment register loads. FIG. 9 shows the three level hierarchy of main memory 900, processor's data cache 910 and processor's descriptor cache 920 which exist when a descriptor cache 920 is introduced into a microprocessor. It should be apparent to those skilled in the art that mechanisms must be employed at each level to ensure the descriptor data maintained at one level is consistent with the descriptor data in the previous level.
As will be described, the present invention discloses an improved memory management system for a computer, where cache coherency between a descriptor cache and a data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit coupled to a data cache is set for a descriptor contained in a data cache line indicating the same unscrambled descriptor is also cached in the descriptor cache. Thus the inclusion bit indicates an association between the data cache line and the descriptor cache. Whenever data in the data cache with an inclusion bit set is altered, modified, or swapped out, the entire descriptor cache is flushed to reflect the fact that the descriptor contained in the descriptor cache is no longer valid or the association is no longer valid. As such, the inclusion bit maintains cache coherency between the descriptor cache and data cache. In turn existing hardware caching mechanisms maintain cache coherency between the data cache and the descriptor table in main memory.